1. Field
Exemplary embodiments of the present invention relate to a semiconductor device fabrication technology, and more particularly, to a semiconductor device including buried gates (BG) and a method for fabricating the same.
2. Description of the Related Art
As semiconductor devices become smaller in size, a semiconductor device may not be able to realize diverse device characteristics. As design rules are less than approximately 40 nm, the formation of a gate structure, a bit line structure, and a contact structure may have technical limitations. Even if such structures are formed, the desired device characteristics may not be achieved. To achieve the desired device characteristics, semiconductor devices may form buried gates (BG) in a substrate.
FIG. 1 is a cross-sectional view illustrating a conventional semiconductor device including buried gates.
Referring to FIG. 1, the conventional semiconductor device with buried gates includes an isolation layer 12 that defines an active region 13 over a substrate 11. The substrate includes a cell region and a peripheral region. In the cell region of the substrate 11, each buried gate includes a trench 15, a gate insulation layer (not shown), a gate electrode 16, and a gate hard mask layer 17. Over the substrate 11, landing plugs 14 are formed. An isolation layer 12 is formed to isolate the landing plugs 14 from another and to isolate the landing plugs 14 from the buried gates. In the peripheral region of the substrate 11, peripheral gates 21 are formed, and spacers 22 are formed on the sidewalls of each peripheral gate 21. Each peripheral gate includes a peripheral gate insulation layer 18, a peripheral gate electrode 19, and a peripheral gate hard mask layer 20. An inter-layer dielectric layer 23 is formed over the substrate 11, and a storage node contact plug 25 and a cell bit line 28 are formed in the inter-layer dielectric layer 23 of the cell region. A portion of a peripheral bit line 31 is coupled with the peripheral gate electrode 19 and formed in the inter-layer dielectric layer 23 of the peripheral region, while a portion of the peripheral bit line 32 is formed above the inter-layer dielectric layer 23. FIG. 1 also illustrates a cell bit line hard mask layer 29, and a peripheral bit line hard mask layer 33.
According to the conventional technology, the peripheral bit line 32 is disposed over the inter-layer dielectric layer 23 of the peripheral region. As a result, subsequent processes become complex and procedurally more difficult. More specifically, step height is inevitably formed between the cell region and the peripheral region because the peripheral bit line 32 is formed over the inter-layer dielectric layer 23. The step height makes the subsequent processes of forming an inter-layer dielectric layer covering the peripheral bit line 32 in the peripheral region and forming storage nodes in the cell region be complicated, and increases the procedural difficulty. Also, the step height between the cell region and the peripheral region cracks an etch stop layer (not shown) interposed between the inter-layer dielectric layer 23 and a mold-forming insulation layer (not shown) for forming a mold, and damages the existing substrate structure during a subsequent dip-out process.